Numerous electrically conductive structures are utilized in semiconductor devices. For instance, conductive lines are utilized in semiconductor constructions for interconnecting circuit elements. It is common to form large grids of conductive lines associated with memory arrays, with the lines being configured for providing access to individual memory devices of the arrays. Conductive lines can also be utilized peripherally to the memory arrays to interconnect peripheral circuitry, as well as to connect peripheral circuitry to the memory arrays. Additionally, conductive lines can be used to provide electrical access between circuitry associated with a semiconductor substrate (i.e., circuitry associated with a semiconductor die), and circuitry external to the semiconductor substrate. Various conductive lines can correspond to so-called metal (I), metal (II), metal (III), metal (IV), metal (V), etc. layers.
A continuing goal of integrated circuit fabrication is to increase the density of integration, which leads to a corresponding goal to pack an ever-increasing number of conductive structures (such as lines) into ever-decreasing space. This leads to challenges in conductive structure fabrication, and it is desirable to develop new methods for conductive structure fabrication which can address such challenges.
Another goal in semiconductor device fabrication is to reduce the costs associated with device fabrication while maintaining or increasing throughput. For this additional reason, it is desired to develop new methods for fabrication of conductive lines.